Key Dates

Registration

Early Bird Discount:
September 10th, 2017

Poster Submission

via EasyChair
September 15th, 2017

Notification of Authors

September 30th, 2017

Previous Schools

2016, Montreal, Canada
2015, Puebla, Mexico
2014, Bariloche, Argentina
2013, Moscow, Russia
2012, Ansan, South Korea
2011, Toulouse, France
2010, Sao Jose dos Campos, Brazil

Sponsors

Spectrum Aerospace Research Corporation

Technische Universität München TIMA IEEE CASS

Leibniz Rechenzentrum

barVARia


Program

The school takes place on October 23rd - 26th, 2017. Click Here for Downloadable Pogramm.
Abstracts and short descriptions for the invited talks can be downloaded here.

DAY 1 - Monday 23rd October


8:00 Registration


9:00 Opening Remarks

Pascal Fouillat (IMS, France) Raoul Velazco (TIMA, France)

9:05 Opening Local Chair

Jaime Estela (Spectrum Aerospace Technologies, Germany)

9:15 Technical Program Overview

Otmane Ait Mohamed (Concordia Univ., Canada) Martin Canales (Spectrum Aerospace Technologies, Germany)

9:20 Space and Earth Radiation Environments. Key Space Weather Issues in the framework of Nanosatellites


Marcelo Famá (ARSAT & CNEA, Argentina)

10:30 Coffee-Break and Poster Session


11:00 Single Event Effects (SEE): Mechanisms and Classifications


Steve Buchner (NRL, USA)

The fundamental mechanisms responsible for non-destructive and destructive Single-Event Effects in ICs will be described in detail. This will include the interactions of ions with the constituent materials of the IC, the response of individual transistors to the disturbance, and the effect on the operation of the IC. The evolution of the threat with device scaling will be addressed.

12:00 Electrical, Electronic and Electromechanical (EEE) Parts in the New Space Paradigm:


When is Better the Enemy of Good Enough?

Ken A. LaBel (NASA, USA)

As the space business rapidly evolves to accommodate a lower cost model of development and operation via concepts such as commercial space and small spacecraft (aka, CubeSats and swarms), traditional EEE parts screening and qualification methods are being scrutinized under a risk-reward trade space. In this presentation, two basic concepts will be discussed: The movement from complete risk aversion EEE parts methods to managing and/or accepting risk via alternate approaches; and discussion of emerging assurance methods to reduce overdesign as well emerging model based mission assurance (MBMA) concepts. Example scenarios will be described as well as consideration for trading traditional versus alternate methods.

13:00—14:30 Lunch



14:30 Single Event Effects Test Methods


Konstantin Tapero (TRINITI, Russia)

The lecture presents an overview of main types of single event effects (SEE), basic characteristics of sensitivity of devices and integrated circuits to SEE and existing standards and guidelines for testing with the use of heavy ion and proton accelerators. Basic requirements for both heavy ion and proton testing will be considered in detail including requirements for the energy of ions, their linear energy transfer (LET) and the range in semiconductor, recommendations for choosing the flux and fluency of ions, requirements for beam control during testing. Also, the lecture gives information about the specifics of testing for different types of SEE, such as: an impact of temperature and electrical bias conditions on the test results; recommendations for choosing test patterns during testing; advantages and disadvantages of static and dynamic testing; an impact of total ionizing dose effects on test results; specifics of testing for destructive types of SEEs and others. In addition, the lecture presents some recommendations for choosing the SEE test algorithm depending on the purpose and required result of testing.

15:30 SEE and TID effects on VLSI devices (ASIC and FPGA)


Luca Sterpone (POLITO, Italy)

Radiation effects on VLSI technology are provoked when radiation particles such as neutrons, protons or heavy ions hit a sensitive region of the integrated circuits. Due to the progressive technology scaling, VLSI devices are becoming, more and more vulnerable to Single Event Effects (SEEs) and are subject to cumulative ionizing damage known as Total Ionization Dose (TID). This talk will firstly describe the state-of-the-art methodologies used for analyzing the impact of radiation effects on modern FPGAs and ASICs by means of Computer Aided Design (CAD) tools and secondly, it will describe the state-of-the-art CAD design techniques for their mitigation.

16:30 Coffee break and Poster Session



17:00 Accurate Abstraction and High Level Modeling and Validation of SEE in Electronic Systems


Otmane Ait Mohamed (Concordia Univ., Canada)

In this talk, we will discuss the practical use of formal based techniques, such as SAT, SMT and probabilistic model checker to analyze SEEs at logical and higher abstraction levels. Through examples, we will illustrate each approach and its benefits.

18:00 End of first day activities



DAY 2 - Tuesday 24 October

8:00 Registration



8:30 COTS in Space: Constraints, Limitations and Disruptive Capability


Michel Pignol (CNES, France)

9:30 Space-COTS: Qualified commercial components for space


Jaime Estela (Spectrum Aerospace Technologies)

Commercial electronics compared to their space qualified counterparts are increasingly proving to be fit for use in space. High performance and reliability together with reduction of qualification costs and less testing time play an important role in the development of the space market. Space- COTS are commercial components qualified for small satellite missions, which support the NewSpace technology development.

10:30 Coffee-break and Poster Session


11:00 COTS for Deep Space Missions


Hans-Jürgen Sedlmayr (DLR-RM: Institute of Robotics and Mechatronics, Germany)

The usage of COTS in Deep Space Missions might be a risk for the mission. But sometimes are radiation tolerant parts not feasible due to space or performance requirements. This talk gives an brief overview of the usage of COTS in (Deep) Space Missions at the DLR Institute of Robotics and Mechatronics and the associated radiation assurance activities.

12:00 Radiation Hardness Assurance of ATHENA Wide-Field-Imager


Dr. Markus Plattner (Max Planck Institute for extraterrestrial Physics, Electronics Department, Germany)

The Max-Planck-Institute for Extraterrestrial Physics (MPE) looks back on several decades of satellite instrumentation. XMM-Newton, Herschel PACS, eRosita, EUCLID-NISP and ATHENA are science Missions wherein MPE has been or currently is payload provider. The Wide-Field-Imager, one of two scientific instruments on-board ESA's next generation X-Ray observatory ATHENA, is chosen to exemplify how up-to-date techniques and methodologies are implemented in a payload development project in order to assure radiation hardness. Characterization of radiation environment, simulation of radiation load, selection of materials and components and measures for radiation hardening are described in this workshop presentation.

13:00—14:30 Lunch



14:30 EMI and Ionizing Radiation Effects on ICs: the need for combined tests


Fabian Vargas (PUCRS, Brazil)

15:30 Laser Testing Laser Simulation Test Possibilities and Facilities


Pascal Fouillat (IMS, France) and Dale McMorrow (NRL, USA)

16:30 Coffee-break and Poster Session


17:00 Hardening-by-Design Techniques for Analog and Mixed-signals


Daniel Loveless (University of Tennessee, USA)

This presentation overviews basic and state-of-the-art approaches for the mitigation of single-events in analog and mixed-signal circuits, provides some examples of hardened circuits, and classifies the techniques based on the fundamental mechanisms of hardening. The primary focus of the presentation will be on layout and circuit-level approaches to single-event hardening.

18:00 End of second day activities



DAY 3 - Wednesday 25th October


8:00 Registration



9:00 Radiation Effects Hardness Assurance


Steve Buchner (NRL, USA)

The approach used to ensure that parts will meet performance requirements for a mission operating in a radiation environment will be discussed. A particular mission will be used to illustrate the method as applied to total ionizing dose, displacement damage dose and single event effects.

10:00 System Hardening and Real Applications (Part 1)


Michel Pignol (CNES, France)

10:30 Coffee-break and Poster Session



11:00 System Hardening and Real Applications (Part 2)


Michel Pignol (CNES, France)

12:00 Development of a Hardened 150nm Standard Cell library


João Baptista dos Santos Martins (SMDH / UFSM, Brazil)

13:00 —14:30 Lunch



14:30 Industrial visit to the SuperMUC Petascale System



20:00 Gala dinner in Munich



DAY 4 - Thursday 26th October


8:00 Registration

8:30 Microprocessor testing: characterization tests, mitigation


Heather Quinn (LANL, US)

9:30 New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective


Melanie Berg (AS & D Inc. in support of NASA/GSFC)

Technology is changing at a fast pace. Transistor geometries are getting smaller, voltage thresholds are getting lower, design complexity is exponentially increasing, and user options are expanding. Consequently, reliable insertion of error detection and correction (EDAC) circuitry has become relatively challenging. As a response, a variety of mitigation techniques are being implemented. They range from weaker EDAC circuits that save area and power to strong mitigation strategies that come as a great expense to the system. Regarding FPGA and ASIC EDAC insertion, there is no “one-solution-fits-all.” The user must be aware of plethora of concerns. As an example, each FPGA device-type requires a different mitigation strategy for various reasons. This presentation will focus on the susceptibilities of a variety of FPGA types and ASICs in the avionics and space environment. In addition, the user will be provided information on what are the optimal mitigation strategies per FPGA and ASIC. Internal device component mitigation versus system level mitigation will also be discussed.

10:30 Coffee break and Poster Session



11:00 Mitigating SEU and MBU Using Backward Error Recovery Approach in SRAM Based FPGA


Fakhreddine Ghaffari (ETIS, France)

The electric vehicle motor control application represents a highly aggressive environment due to the level of electromagnetic fields, the temperature, and the ionizing radiation. When an FPGA is used in such environment, it is of paramount importance to ensure the correct execution of the implemented design to avoid damages. In fact, FPGAs are susceptible to their execution environment which can induce runtime faults. The aim of this presentation is to present an analysis of that environment effects on the FPGA and to establish a fault model giving the error rate of the application with respect to the specified environment. Then, mitigation solutions are described in order to ensure the correct execution of the application implemented in the FPGA.

12:00 Non-volatile Memories and Their Space Applications


Alessandro Paccagnella (University of Padova, Italy)

Non-volatile memories (NVM) are fundamental components of electronic systems and NAND Flash are actively pushing Moore’s law to its scaling and integration limits, including 3D integration. Ionizing radiation effects represent a challenge for the reliability of such devices in several fields, not only in space, but also in avionic and terrestrial applications. A NVM is based on a complex chip integrating memory arrays and peripheral circuits, which offer different sensitivities to total ionizing dose (TID) and single event effects (SEE). After introducing the space radiation environment met by NVM and the corresponding failure mechanisms, this presentation will focus firstly on the basic radiation effects on NVMs, with a particular attention to Flash memories. We’ll illustrate the physical mechanisms responsible for the charge loss from floating gate cells exposed to ionizing radiation and the onset of bit failure. Then, this tutorial will discuss the more recent findings on the effects of total ionizing dose and Single Event Effects on floating gate cells and the peripheral circuitry of Flash memories.

13:00 —14:30 Lunch



14:30 Fault Injection Methodologies


Luis Entrena (UCIII, Spain)
Fault injection is a widely used method to evaluate fault effects and error mitigation in a design. While not a replacement for standard Radiation-Hardness Assurance methodologies, it can provide valuable information in a quick and inexpensive manner. Moreover, recent developments have improved performance by several orders of magnitude, thus enabling the realization of extremely large fault injection campaigns. Today, fault injection can be used to forecast the expected circuit behavior in the occurrence of SEUs and SETs, validate error mitigation approaches and detect weak areas that require error mitigation. This talk will review the most relevant fault injection methods, covering software-based techniques, simulation techniques and FPGA-based emulation techniques. Recent advances for SET and MCU emulation will also be presented.

15:30 Error-rate Prediction for Programmable Circuits: Methodology, Tools and Studied Cases


Raoul Velazco (TIMA, France)

This presentation describes a method devoted to SEU error-rate prediction for processor-based architectures. The proposed method combines results issued from fault-injection, performed at circuit by means of CEU (Code Emulated Upsets), to those issued from radiation ground tests. It allows predicting error rates without requiring radiation ground-tests for future applications. The approach was successfully applied to processors and FPGAs and is illustrated by three representative case-studies.

16:30 Coffee break and Poster Session



17:00 Multi and Many core Processors: Validation by radiation tests of Robust applications benefitting of the multiplicity of cores


Nacer Zergainoh (TIMA, France)

This work evaluates the SEE static and dynamic sensitivity of a single-chip many-core processor having implemented 16 compute clusters, each one with 16 processing cores. A comparison of the dynamic tests when processing-cores cache memories are enabled and disabled is presented. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the MPPA-256 many-core processor manufactured in TSMC CMOS 28HP technology.

18:00 Concluding remarks


Raoul Velazco (TIMA, France) & P. Fouillat (IMS, France)